PandaDAQ: FPGA expansion for the OMAP 4 Pandaboard

Texas Instruments has produced some inexpensive development boards to showcase their OMAP ARM systems-on-a-chip (SoC): first the OMAP 3 Beagleboard, and more recently the OMAP 4 Pandaboard. While intended primarily for software developers, their low power consumption and easy hardware expandability has made them popular for everything from home Linux servers to robot projects.

When TI announced a contest for Pandaboard project ideas last spring, I decided to enter. I had been looking for an excuse to learn how to design with FPGAs, and the platform still lacked an FPGA expansion board comparable to Eric Brombaugh’s Beagle FPGA project. I was also in need of an inexpensive data-acquisition solution for Linux; thus the PandaDAQ was born.

Design

PandaDAQ features:

  • one Xilinx Spartan 6 in 144-pin QFP (XC6SLX9-2TQG144C)
  • plenty of digital I/O at 3.3 and 1.8 volts
  • up to two Analog Devices AD7606 16-bit A/Ds with eight channels each
  • up to two Analog Devices AD5064 16-bit D/As with four channels each
  • choice of 5x3.2-mm, 1.8-volt clock oscillator
  • battery-friendly switching power supply
  • optional ublox NEO-6 GPS module with ext antenna and kHz clock output
  • optional OCXO (Pletronics 26 MHz, 5V, 14-pin DIP from EBay)

Power supply

The board requires several voltage rails:

Voltage (V) Used for Est. current (mA) Source
1.2 FPGA core (Vccint) 500 SMPS (TPS62420)
1.8 FPGA I/O, I2C devices (configuration pins and GPMC) 100 Expansion connector
2.5 FPGA Vccaux 100 Linear regulator (TPS73625) from switcher 3.3V
3.3 FPGA I/O, A/D and D/A digital interfaces 200 SMPS (TPS62420)
5.0 A/D and D/A, OCXO 120 Pandaboard expansion connector

A switching power supply adds complexity and risk, but given the low voltages required, the efficiency improvement is substantial. The TPS62420 is is a dual switcher with few external components which can supply up to 1A for the 1.2V Vccint and up to 600 mA on the combined 3.3V and 2.5V rails.
This is the trickiest part on the board to solder, coming in a QFN package with ground paddle.

The Pandaboard spec does not specify a limit for power drawn on the 1.8V expansion pin, but comments on the mailing list suggest 100 mA is OK, and everything seems to work.

According to Xilinx, Spartan 6 has no sequencing requirements. The 1.8V Vcco will be powered as soon as the board is plugged in, but will draw less than 1 mA of quiescent current while the other supplies are off.

FPGA configuration

PandaDAQ follows the Beagle FPGA strategy of SPI-based slave-serial configuration, coordinated with the help of an I2C parallel port (TCA6408A ). Spartan 6 simplifies the design by allowing configuration at 1.8V, eliminating some level shifters. Extra port-expander pins are assigned to the power-supply
enables, the Spartan-6 sleep/wake pins, and an LED.

A major advantage of the Pandaboard is the availability of the GPMC (general-purpose memory bus) on its expansion pins. This permits a memory-mapped register interface and high-bandwidth data transfers to the host.

Two of the Spartan-6 I/O banks are taken up by the 1.8-volt GPMC, configuration I/Os, and clocks. The other two run at 3.3V and support the A/Ds, D/As, and 0.1-inch I/O expansion headers. The pinout of the headers matches the Digilent standard. Four of the pins are brought out to RF connectors (two SMA and two u.fl).

Clocking and GPS

A standard 5x3.2-mm four-pad footprint accommodates a range of 1.8-volt oscillators. The one I’m using is 80 MHz.

The optional GPS module is intended for accurate time-stamping or position logging of acquired data. After considering some cheaper alternatives, I settled on the ublox NEO 6 series for a couple of reasons. First, it is well documented, to a much higher standard than the comparable SiRF/CSR-based modules. Second, the basic NEO 6Q offers a programmable
time-pulse output from 1 Hz to 1 kHz, and the pin-compatible NEO 6T supports time-pulse to 10 MHz. Together with the Pletronics OCXO, this could enable a half-way decent GPS disciplined oscillator (GPSDO), for very accurate time and frequency measurements.

A/D and D/A

The 16-bit AD7606s offer eight single-ended channels each. These can be sampled simultaneously or in groups at up to 200 kHz, although that rate is only for oversampling. (A fixed antialiasing filter rolls off at 20 kHz.) There are other pin-compatible parts in this family, with up to 18-bit resolution and differential inputs.

The FPGA connects to the serial data lines and many control lines of each AD7606, allowing it to start conversions, choose the oversampling ratio, etc. independently on each chip. A precision reference (ADR421) is designed in, but can be left unpopulated if the internal references are adequate. A jumper selects internal vs. external reference.

The 16-bit AD5064-1s are daisy-chained on the same serial interface. Each one provides four analog outputs, which are wired to a single header, together with the reference inputs and 5V supply. The reference inputs can be connected to 5V for non-critical applications, or driven from a user-supplied voltage reference.

Construction

PCB layout

144-QFP power routing on two layers

I decided to try a two-layer design for Laen’s DorkbotPDX PCB service. This necessitated a lot of funky (and non-optimal) layout of the four power rails plus ground at the FPGA. It also took a really long time in the archaic “pcb” software package; in hindsight, I probably should have sprung for the four-layer service. Still, everything appears to work. I did run into some FPGA configuration issues due (I think) to improper routing of the CCLK net: There are three vias between the expansion connector and the FPGA, and only part of the line is over a ground plane.

Board bring-up

22 Jan 2012: Switching power supply OK

The 1.2/3.3-volt dual switcher (TPS62420), a 10-pin QFN with ground pad, is the most difficult part to install. The following advice was written based on my experience with a Metcal temperature-controlled soldering iron; using a toaster-oven, skillet, or hot-air method with solder paste may be easier:

  1. Make sure you think ahead and don’t solder anything which could block or make it difficult to solder later parts. I think it’s best to get the TPS62420 in place first. It’s easier to add the two back-side 0805’s after the IC pins are soldered, so it won’t move even if you re-melt the ground pad.
  2. When you tin the ground pad on the board (and possibly on the part itself), be stingy with the solder. There’s a risk of it squishing against the signal lands, creating a short.
  3. Because of the thermal vias, I found I could not melt the ground pad from the tabs sticking out on the top side of the board. I had to heat from underneath (the vias come out on an 0805 pad on the bottom). All while keeping the board level and right-side up. Tricky!
  4. Once the ground pad is done, the usual drag-soldering technique works fine—use lots of flux. It helped to switch to a fine-point tip, though, as the chisel I normally use for drag soldering has trouble reaching into the pcb-land / package corner.
  5. De-flux thoroughly (I use 90% isopropanol) and allow to dry for a few hours before testing. There are some high-Z sense lines where ~1Mohm shunt would be enough to throw it off.

The TPS73625 LDO (SOT223-6 package) regulates the 2.5-volt Vccaux rail from the 3.3-volt switcher output. If using board version 1.0, three pins must be bent up and fly-wired to the correct pads due to a layout error.

7 Feb 2012: I2C works

Note: A kernel patch may be necessary if there are i2c timeout errors when probing with i2cdetect.

With the TCA6408A, CAT24C01, and surrounding components installed, I can toggle red LED101 and control the power supply via i2cset commands.

20 Feb 2012: SPI loopback works

With McSPI1 SIMO shorted to McSPI1 SOMI on the expansion connector, spidev_test -D /dev/spidev1.0 shows identical read/write bytes. I followed the instructions at http://elinux.org/BeagleBoard/SPI to build a kernel with the SPI device added to the board file (obviously, substituting “panda” for “beagle”, and bus_num=1). No pin-mux changes were required as these pins were already assigned to McSPI1 function on the Pandaboard.

27 Feb 2012: FPGA configures successfully

Drag soldering with the Metcal hoof tip made installing the 144-pin QFP packages relatively painless. The expansion headers get in the way on one side, but that’s unavoidable if testing I2C before the FPGA is installed (a good idea).

Board with FPGA mounted

The decoupling capacitors on the back take a while to install. Under the magnifier, the 0402s weren’t as bad as I feared, but they’re easy to lose if you’re not careful.

After some false starts, I was able to configure the FPGA with a test image (blinking LED302 / LED303). PandaDAQ lives!

I am using a modified version of Eric Brombaugh’s bfpgatool to twiddle the FPGA configuration pins, read the Xilinx bit file, and send the image over McSPI1. For some reason I am getting an unexpected INIT low before the transmission is 100% complete. This causes a fatal error in the configuration tool, but by this point the FPGA has configured just fine.

Configuration fails at SPI clock rates above 500 kHz, and in retrospect, I see several potential issues with CCLK (the FPGA configuration clock, connected to McSPI1_CLK): The trace impedance is anything but controlled, with three vias and routing that crosses the edges of ground and power planes. Also, the series-AC termination values need optimization. More on this later…

Errata

  • U202 (TPS73625) has wrong pinout. Fixed in v1.1.
  • R303, the HSWAPEN pulldown, should be 1k. Fixed in v1.1 (but it can be left open instead, if you don’t mind pins floating prior to configuration).
  • CCLK net (McSPI1_CLK on Panda side) has vias and other impedance discontinuities. Leaving the AC termination open actually improves reliability. Set R307 to 150 ohms in v1.1.
  • OMAP4 McSPI1 SOMI, a 1.8-volt signal, is connected to FPGA pin 74 in a 3.3-volt logic bank. This signal is not required for programming, and should be cut (or pin 74 lifted) on the v1.0 board. Connected to pin 47 instead in v1.1.
  • No bare copper under board-edge SMA connectors (use fine sandpaper to remove soldermask).
  • Expansion connectors should have been flipped over, to have the bottom side of the PandaDAQ mate with the bottom of the Pandaboard. (As it is, long headers are necessary to let the Pandaboard clear the top side of the PandaDAQ.) Lesson learned, but no planned fix.